1. Field of the Invention
The present invention relates to a transistor structure which may improve a gate breakdown voltage of a thin film transistor using a thin polycrystalline silicon layer as a channel layer, and to a manufacturing method thereof.
2. Description of the Background Art
A so-called thin film transistor (TFT) is one type of insulated gate field effect transistors configured to have a semiconductor thin film formed on an insulating substrate and a channel region provided in this thin film.
FIG. 16 shows a view of cross-sectional structure of a conventional thin film transistor, which is disclosed, for example, in International Electron Device Meeting, 1988. Referring to FIG. 16, a conventional thin film transistor includes a gate electrode 41 of a polycrystalline silicon layer formed on the surface of an insulating substrate or insulating layer 40. A gate insulating layer 42 such as of an approximately 250-thick oxide film is formed on surfaces of insulating substrate 40 and gate electrode 41. A polycrystalline silicon layer 43 with a thickness of approximately 30 nm is formed on the surface of gate insulating layer 42. Polycrystalline silicon layer 43 includes a pair of source/drain regions 45, 45 and a channel region 44 formed therebetween.
A manufacturing process of a thin film transistor will now be described. FIGS. 17 to 20 are views of cross-sectional structures showing in order steps of a manufacturing process of a thin film transistor shown in FIG. 16.
First, as shown in FIG. 17, after forming a polycrystalline silicon layer on the surface of insulating substrate 40, a photolithography method and an etching method are used to pattern the layer in a predetermined shape. According to this process, gate electrode 41 is formed.
Second, as shown in FIG. 18, an approximately 40 nm-thick oxide film, for example, is deposited on the whole surface using a low pressure CVD (Chemical Vapor Deposition) method. This oxide film constitutes gate insulating film 42.
Next, as shown in FIG. 19, approximately 30 nm-thick polycrystalline layer 43 is deposited on the surface of gate insulating film 42 using a low pressure CVD method.
Finally, as shown in FIG. 20, a resist mask 50 is formed on a region to be a channel of polycrystalline silicon layer 43. Impurity ions 51 are ion-implanted into polycrystalline silicon layer 43 using resist mask 50 as mask, thereby forming a pair of source/drain regions 45, 45. Then the implanted ions are activated by a thermal treatment.
According to the above described process, a thin film transistor shown in FIG. 16 is provided.
However, since a conventional thin film transistor is configured by source/and drain regions 45, 45 of a single layer having a higher concentration, a steep impurity concentration distribution is provided in boundaries between source/drain regions 45, 45 and channel region 44. As a result, when a predetermined voltage is applied between source 45 and drain 45 regions, a field concentration occurs in the vicinity of the drain region. In addition, polycrystalline silicon layer 43 includes many defect levels such as in a grain boundary of a crystal. Therefore, when a field concentration occurs in the vicinity of the drain region, a field emission of carriers is accelerated through these defect levels, resulting in a problem that a drain leakage depending on a drain voltage increases.